♦读周期
Read cycle

电平高于VIH(min)且 电平低于VIL(max)时，操作定义为读周期。读操作访问时间定义为片选信号、输出使能和地址中较晚有效信号到来的时间和输出有效数据的时间之差。
When level is higher than VIH(min) and level is lower than VIL(max), the operation is defined as read cycle. Read operation access time is defined as difference between arrival time of valid chip select signal, output enable signal and address signal that arrives latest, and the time of valid data output.

读操作方式1为地址变化读取，如图7-1所示，是在片选有效且 时由输入地址的变化触发的。当满足指定的时间条件tAVQV时，DQn(7:0)会输出有效数据。整个周期内输出都保持有效状态。只要片选信号和输出信号都处于使能状态，地址的输入可以以最小读周期tAVAV的频率变化。
Read Operation Mode 1 is address change read, as shown in Fig. 7-1, which is triggered by address changes when chip select is valid and . When the specified time condition tAVQVis met, DQn(7:0) will output valid data. Output maintains valid throughout the whole cycle. As long as chip select signal and output signal are both enabled, the address inputs can vary with the frequency of the minimum read cycle tAVAV.

读操作方式2为片选控制读取，如图7-2所示，是在 ，且地址在整个周期内维持稳定的情况下由 信号触发。当满足指定的时间条件tETQV时，可访问到A(18:0)给出的地址并在DQn(7:0)上输出有效数据。
Read Operation Mode 2 is chip select control read, as shown in Fig. 7-2, which is triggered by signal when and on condition that the address maintains stable throughout the whole cycle. When the specified time condition tETQVis met, the address given by A(18:0) can be accessed and valid data will be output on DQn(7:0).